Programmable logic devices exist as a well-known type of integrated circuits that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic devices, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure,are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
An FPGA or other integrated circuit is conventionally tested by connecting it to a socket coupled to probe printed circuit board (PCB) or card, prototype card or other testing or tester card. Externally accessible input and output pins of such an integrated circuit are coupled to a printed circuit board for coupling to a tester.
However, an embedded device may not have directly accessible external pins after it is embedded. For example, a wafer having a plurality of microprocessor cores formed on it may be subsequently processed to form respective FPGAs in contact with such a microprocessor core. The microprocessor core may no longer be directly accessible owing to interconnect layers and dielectric layers, among others, extending over the microprocessor core.
This presents a problem for testing the microprocessor core. Even if a microprocessor core were tested prior to FPGA fabrication, it would still need to be retested after such FPGA fabrication. To test such a microprocessor core, input and output pins of the combined FPGA and microprocessor core device need to be used to access internal pins of the microprocessor core device. However, the microprocessor core device may comprise more inputs and outputs than the device in which it is embedded. Moreover, extending inputs and outputs of the microprocessor core device to provide additional inputs and outputs of the combined device would necessitate significant additional interconnect routing and an increase in package size.
Accordingly, it would be desirable and useful to provide method and apparatus for testing an embedded device without increased package size. Moreover, it would be desirable and useful to provide method and apparatus to test an embedded device without additional circuitry even though an integrated circuit manufactured with such an embedded device has fewer input and output pins than the embedded device.